Cycles read

Used DDR3 4GB Ram (Laptop) Price in Pakistan 1)Data rate:1333MHz/1600MHz (max). 2) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8Vpower supply for DDR II products 3) Double-data-rate architecture, two data transfers per clock cycle. 4) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be Used in capturing data at the receiver 5) Data inputs and outputs are synchronzed with DQS. 6) DQS is edge aligned with data for read, center aligned with data for write. 7) Differential clock inputs (CK and CK). 8) DLL aligns DQ and DQS transitions with CK transitions 9) Commands entered on each positive CK edge: Data and data mask referenced to both edges of DQS. 10) Four internal banks for concurrent operation (component). 11) Data mask(DM) for write data. 12) Auto precharge option for each burst access 13) Programmable burst length: 2, 4, 8 14) Programmable/CAS latency (CL): 3 15) Programmable output driver strength: Normal/weak 16) Refresh cycles: (8192 refresh cycles/64ms). 17) 7.8US maximum average periodic refresh interval. 18) Posted CAS by programmable additive latency for better command and data bus efficiency 19) Off-chip-driver impedance adjustment and on-die-termination for better signal quality. 20) DQS can be disabled for single-ended data strobe operation 21) 2 variations of refresh 22) Auto refresh 23) Self refresh.